The present invention relates to a data transfer control circuit for transferring data between, for example, a personal computer and a card installed in the personal computer.
A card installed in a personal computer will be referred to below as a PC card. FIG. 1 shows the relevant parts of a conventional PC card 10 and its electrical interconnections to the personal computer (PC) 1. The interconnections are made by mounting the PC card 10 in a socket (not visible) in the personal computer 1.
The interconnections include an address bus 11, a data bus 12, a plurality of control signal lines 13, and an interrupt signal line 14. The address bus 11 supplies address signals SA{10:0} (that is, signals SA10 to SA0) from the socket to an address decoder 15, to a plurality of universal asynchronous receiver-transmitters (UARTs) 16-0, 16-1, . . . , 16-7, and to circuits such as an internal memory or input-output circuit (not visible) in the PC card 10. The address decoder 15 receives and decodes address signals SA{10:3}, thereby generating chip enable signals CE0 to CE7 for the UARTs 16-0 to 16-7. The UARTs 16-0 to 16-7 receive the remaining address signals SA{2:0}. When one of the chip enable signals CE0 to CE7 is active, the corresponding UART is connected to the address bus 11, data bus 12, and control signal lines 13. The UARTs carry out asynchronous serial data transfer.
The UARTs 16-0 to 16-7 all have the same internal structure, including a receive-send data register RSDAT, an interrupt enable register IER, an interrupt identification register IIR, a line control register LCR, a modem control register MCR, a line status register LSR, a modem status register MSR, and a scratch register SCR. These eight registers are selected by address signals SA{2:0}. The selected register can be accessed via the data bus 12 under control of a read control signal RD and a write control signal WR, which are carried on two of the control signal lines 13.
While transmitting or receiving serial data, the UARTs may generate interrupt requests by driving respective interrupt signals INT0, INT1, . . . , INT7 to the low logic level. When requesting an interrupt, a UART indicates the interrupt source (the reason for the interrupt request) by setting a bit or bits in its interrupt identification register IIR.
The above interrupt signals INT0 to INT7 and another interrupt request signal INTR, which originates from other circuitry (not visible) in the PC card 10, are received by an AND gate 17. The AND gate 17 sends a single interrupt signal INT to the personal computer 1 on the interrupt signal line 14. When no interrupt is requested, interrupt signals INT0, . . . , INT7, INTR are all at the high logic level, so the interrupt signal INT output by the AND gate 17 is also at the high logic level. When one of the interrupt signals INT0 , . . . , INT7, INTR goes low to request an interrupt, the interrupt signal INT output from the AND gate 17 also goes low, and the personal computer 1 is notified of the interrupt request. The personal computer 1 then reads the interrupt identification registers IIR in the UARTs in turn to find the UART from which the interrupt request originated, and carries out processing as required by the interrupt.
A problem with this type of PC card is that there is often a delay in responding to an interrupt request, because before the personal computer 1 can identify the interrupt, it may have to read the interrupt identification registers of several UARTs. If the interrupt was caused by the INTR signal, the personal computer 1 must search through the interrupt identification registers of all the UARTs in order to determine that the interrupt request did not originate in any of the UARTs and is therefore due to the INTR signal.
It is also inconvenient that in order to disable interrupts from a plurality of UARTs, the personal computer 1 must access the interrupt enable registers of each of those UARTs.